Field of the Invention
Embodiments of the present invention relate generally to integrated circuit chip packaging and, more specifically, to a system with a high power chip and a low power chip.
Description of the Related Art
In the packaging of integrated circuit (IC) chips, there is generally a trade-off between the thermal management of chips and other devices contained in a package and the performance of said devices. Specifically, by locating memory chips, passive devices, and other low-power components of an IC package as close as possible to the central processor unit (CPU) and other high-power devices in an IC package, communication between devices in the IC package is accelerated and packaging parasitics are reduced. However, heat generated by higher-power chips is known to adversely affect memory chips and other devices positioned nearby. Consequently, it is not thermally feasible to stack memory chips and passive devices directly on or under a CPU or other high-power chip when incorporated into a single IC package; such a configuration necessarily limits the power of the high-power chip or risks damage to and/or affects the performance of the memory chips. Including lower-power chips in a single IC package by positioning such chips beside the high-power chips in the IC package is also undesirable, since such a horizontally distributed configuration results in the IC package having an impractically large footprint as well as having a longer interconnect path between the low-power chips and the high-power chips. As the foregoing illustrates, there is a need in the art for an IC package for a high-power chip and a low-power chip disposed in close proximity to each other that prevents the low-power chip from overheating.